Invited Speakers

If you are interested in speaking at this event, please submit your abstract by 1 September 2023

Prof. Asen Asenov, University of Glasgow

Asen Asenov (FIEEE, FRSE) received his MSc degree in solid state physics from Sofia University, Bulgaria in 1979 and the PhD degree in physics from The Bulgarian Academy of Science in 1989. As a James Watt Professor in Electrical Engineering and a Leader of the Glasgow Device Modelling Group Asenov directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices. He has pioneered the simulations of statistical variability in nano-CMOS devices including random dopants, interface roughness and line edge roughness. He has over 550 publications and more than 160 invited talks in the above areas.

Abstract: A Methodology for Cryogenic PDK Re-Centering Using Experimental Data and TCAD Simulations

There is great interest in cryogenic CMOS design for interfacing CMOS analogue and digital circuits to the quantum bits (qubits) in the same cryogenic chamber. This can enable proper scaling of the quantum computers, which currently with all cabling going out of the cryostats resemble inverted Christmas trees. An important issue is that the foundry PDKs are designed for room temperature operation only and no foundry PDKs are available for design at cryogenic temperatures. Measurements at cryogenic temperatures can be used to re-center [1] the room temperature PDK to cryogenic temperatures, but it is complicated due to discrepancies between the characteristics of the Typical/Typical (TT) transistors from the foundry PDK and the transistors measured on the silicon chips. The foundry does not guarantee the customer that the fabricated transistors will have the same characteristics as the TT transistors in the PDK. The foundry only guarantees that the transistor characteristics on the fabricated wafers will be in-between the characteristics of the fast/fast (FF) and slow/slow (SS) corner transistor characteristics in the PDK.

This paper outlines the procedures to accurately re-center room temperature foundry PDKs for design at cryogenic temperatures using a combination of experimental cryogenic measurements of CMOS transistors on test chips and TCAD simulations. The methodology delivers PDK quality models for TT, SS, FF, SF and FS transistors and include statistical variability (mismatch). A flowchart summarizing the entire methodology is shown in Fig. 1. The next sections describe the various steps involved.

Fig. 1 TCAD only and TCAD + measurements PDK re-centering methodology.

Dr. Masoud Babaie, Delft University

Masoud Babaie is currently an Associate Professor at the Delft University of Technology, Delft, The Netherlands. His research interests include RF/millimeter-wave integrated circuits for wireless communications and cryogenic electronics for quantum computation.

Dr. Babaie currently serves as a technical program committee (TPC) member of the ISSCC and ESSCIRC conferences. He was a co-recipient of the 2019 IEEE ISSCC Demonstration Session Certificate of Recognition, the 2020 IEEE ISSCC Jan Van Vessem Award for Outstanding European Paper, the 2022 IEEE CICC Best Paper Award, the 2023 IEEE IMS Best student paper award. In 2019, he received the Veni Award from the Netherlands Organization for scientific research.

Abstract: A Cryo-CMOS Receiver for Spin Qubit Gate-Based Readout: from Modelling to Implementation and Verification

This presentation firstly discusses different readout schemes for spin qubits, such as DC readout, radio frequency reflectometry, and gate-based readout. The drawback and benefits of each structure are also compared in terms of scalability, readout speed, and fidelity. For the rest of the talk, the main focus will be on the gate-based readout in which the qubit state can be detected by probing the shift of the resonance frequency of a resonator connected to the readout gate of a double quantum dot (DQD). Since readout fidelity is limited by the achievable signal-to-noise ratio (SNR) obtained within a certain readout time, a theoretical framework is presented to evaluate the effect of various parameters, such as the readout probe power, electronics noise performance, and integration time, on the resonator frequency shift, and the SNR of RF gate-based readout systems. Then, we shift the gear towards the challenges in the design of a cryogenic-CMOS (Cryo-CMOS) receiver for the gate-based readout of spin qubits. Finally, after showing the electrical performance, the cryo-CMOS receiver is used to measure the DQD charge stability diagrams, and quantify the maximum achievable SNR of the gate-based readout architecture. The proposed analytical approach, the developed model, and experimental results will enable designers to optimize the entire readout chain effectively, thus leading to faster, lower-power readout with integrated cryogenic electronics.

Dr Mark Johnson, Quantum Motion Technologies

Mark Johnson is a Senior Quantum Engineer at Quantum Motion Technologies, a UK-based startup dedicated to the development of quantum computing hardware based on silicon technology. Mark completed his PhD at the University of New South Wales in Sydney, where his research focussed on donor-based silicon quantum devices. Now, he designs and validates foundry-made silicon devices for the deployment of electron spin qubits in a highly scalable platform.

Abstract: Rapid characterisation of over 1000 silicon quantum dots

The management and quantification of variability associated with quantum device manufacturing is of primary importance to scale quantum computing systems. High-throughput characterization techniques are hence key to correlate aspects of the manufacturing process and device design with
statistical evidence of device behaviour. Here, we demonstrate a fast characterisation methodology for silicon-based quantum dot devices, the physical host of spin qubits. We combine high-bandwidth radiofrequency reflectometry techniques with an integrated analogue cryogenic multiplexer to
characterise quantum dots devices implemented on an industry standard silicon-on-insulator process. Our optimized approach allows measuring 1024 devices in less than 15 minutes at milliKelvin temperatures. Additionally, our automated parameter extraction routine allows establishing correlations with specific device geometries. Our methodology provides a rapid characterisation technique to assess quantum device variability as well as optimise manufacturing processes & designs.

Dr Gian Salis, IBM Zurich

Gian Salis studied experimental physics at the ETH in Zurich, Switzerland. He received a PhD degree from ETH in 1999 for his research on electron transport in semiconductor quantum structures. His thesis was awarded with the ETH silver medal. From 1999 to 2001, he worked as a post-doc at the University of California in Santa Barbara. Since 2001, he has been a research staff member at the Zurich Lab of IBM Research. He is an expert in semiconductor spintronics and has investigated semiconductor quantum structures with transport, optical and microwave techniques. His current research is focused on building a scalable spin qubit platform based on silicon and Ge/SiGe heterostructures.

Abstract: How are hole-spin qubits in Ge/SiGe heterostructures driven and why do they decohere?

Spin qubits defined in Ge/SiGe heterostructures comprise an attractive candidate for quantum information processing due to their inherent coupling to electric fields enabling fast and scalable qubit control. However, the mechanisms and anisotropies that underlie qubit driving and decoherence are still mostly unclear. In this talk I will report on our recent measurements of the highly anisotropic heavy-hole g-tensor and its dependence on electric fields, allowing us to relate both qubit driving and decoherence to an electric modulation of the g-tensor. We also confirm the predicted Ising-type hyperfine interaction but show that qubit coherence is ultimately limited by 1/f charge noise.

Pablo Cova Farina, TU Delft

Pablo Cova Fariña completed his Master's degree in solid-state physics at the Technical University of Munich. In 2020, he joined the Vandersypen lab in QuTech (Delft), whose main focus is the development of semiconductor-based quantum computing using quantum dot arrays. As a PhD candidate, Pablo's main line of research concerns analog quantum simulations using quantum processors in germanium.

Abstract: Quantum dot ladders for quantum computation and simulation

Analog quantum simulators promise to shed light on current problems in natural sciences before digital, fault tolerant quantum computers reach quantum practicality. Semiconductor gate-defined quantum dot arrays have emerged as a leading platform for both digital and analog efforts. In particular, the natural mapping of these systems to an extended Fermi-Hubbard model opens the possibility to use them to simulate correlated electron phenomena. In our past efforts, we have thoroughly characterized and successfully operated the first germanium 2x4 quantum dot array, using it to explore the physics of charge and spin ladders. Concretely, we first implemented exciton transport through the array, exploiting the naturally occurring Coulomb interaction between the two ladder legs. We track this phenomenon using charge sensing and observe a transition between single charge flow and exciton transport. Furthermore, we performed coherent control of four singlet-triplet qubits along the ladder rungs. We implemented swap oscillations between each nearest qubit pair and were able to transfer a state from one end of the array to the other. In this talk, we will discuss the two aforementioned experiments in detail, while also briefly outlining future experiments we plan to perform on this device. Finally, we will give an overview of other projects that are being carried out in our lab.